1. Field of the Invention
The present invention relates to a tri-state output buffer using a bipolar transistor and MOS transistors (MOSFETs).
2. Description of Related Art
One typical type of conventional tri-state output buffers using a bipolar transistor and MOS transistors is composed of an output NPN transistor having a collector connected to a high voltage of a power supply and an emitter connected to an output line. A base of the NPN transistor is grounded through an input or first MOS transistor having a gate connected to receive an input signal. A second MOS transistor is connected in parallel to the first MOS transistor and a gate of the second MOS transistor is connected to receive a high impedance control signal. In addition, the emitter of the NPN transistor is also connected to the ground through a third MOS transistor having a gate connected to receive the high impedance control signal. Accordingly, the NPN transistor and the third MOS transistor are connected in series between the high voltage of the power supply and the ground.
In the above mentioned construction, when the output of the conventional tri-state output buffer should be brought into a high impedance condition, the second and third MOS transistors are respectively rendered on and off by the high impedance control signal, so that both of the NPN transistor and the third MOS transistor connected in series with the NPN transistor are turned off.
In this condition, if the output line is supplied with a high level signal from another output buffer connected to the same output line, an base-emitter of the NPN transistor is put in a revere biased condition, since the base of the NPN transistor is grounded by the turned-on second MOS transistor and the emitter of the NPN transistor is maintained in a floating condition by the turned-off third MOS transistor.
Here, it should be noted that a base-emitter junction of currently used NPN bipolar transistors has a reverse biased withstand voltage of about 4 V to 4.5 V, and this reverse biased withstand voltage is apt to further decrease with increase in fineness or miniaturization of transistors. On the other hand, the conventional BiMOS tri-state output buffer is often incorporated in a 5-V power supply system which is one of currently widely used standard systems. Therefore, when the base-emitter junction of the NPN transistor of the BiMOS tri-state output buffer is subjected to a high level signal which is higher than the reverse biased withstand voltage and which is supplied from another output buffer, the base-emitter junction of the NPN transistor of the BiMOS tri-state output buffer is broken down, so that a breakdown current flows from the emitter to the base of the NPN transistor of the BiMOS tri-state output buffer.